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An Efficient VLSI Architecture of VLD for AVS HDTV Decoder
VLSI Architecture VLD AVS HDTV Decoder
2010/12/16
!aIn this paper, we present a VLSI design of Variable Length Code Decoder for AVS video standard. As a co-processor of a RISC CPU, the design can decode Fixed Length Code, unsigned or signed k-th Exp-...
An Efficient VLSI Architecture of the Sample Interpolation for MPEG-4 Advanced Simple Profile
Efficient VLSI Architecture the Sample Interpolation MPEG-4 Advanced Simple Profile
2010/12/14
Sample interpolation which has a computationally expensive finite impulse response (FIR) digital filter is one of the key modules in MPEG-4 Advanced Simple Profile (ASP). Normal FIR architectures have...