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A Practicable Timing Attack Against HQC and its Countermeasure
HQC BCH decoding Timing attack
2019/8/8
In this paper, we present a practicable chosen ciphertext timing attack retrieving the secret key of HQC. The attack exploits a correlation between the weight of the error to be decoded and the runnin...
One Bit is All It Takes: A Devastating Timing Attack on BLISS’s Non-Constant Time Sign Flips
Lattice-Based Cryptography Cryptanalysis BLISS
2019/8/7
As one of the most efficient lattice-based signature schemes, and one of the only ones to have seen deployment beyond an academic setting (e.g., as part of the VPN software suite strongSwan), BLISS ha...
QC-MDPC: A Timing Attack and a CCA2 KEM
post-quantum cryptography code-based cryptography QC-MDPC codes
2018/3/12
In 2013, Misoczki, Tillich, Sendrier and Barreto proposed a variant of the McEliece cryptosystem based on quasi-cyclic moderate-density parity-check (QC-MDPC) codes. This proposal uses an iterative bi...
CacheBleed: A Timing Attack on OpenSSL Constant Time RSA
side-channel attacks cache attacks cryptographic implementations
2016/3/2
The scatter-gather technique is a commonly-implemented approach to
prevent cache-based timing attacks. In this paper we show that scatter-gather is
not constant-time. We implement a cache timing att...
Theoretically secure cryptographic algorithms can be vulnerable to attacks due to their implementation flaws, which disclose side-channel information about the secret key. Bernstein's attack is a well...
Lucky Microseconds: A Timing Attack on Amazon's s2n Implementation of TLS
TLS CBC-mode encryption timing attack
2015/12/21
s2n is an implementation of the TLS protocol that was released in
late June 2015 by Amazon. It is implemented in around 6,000 lines
of C99 code. By comparison, OpenSSL needs around 70,000 lines of
...
An Improved Trace Driven Instruction Cache Timing Attack on RSA
public-key cryptography / Instruction cache-timing attacks side channel attack RSA cryptographic algorithm Trace-driven.
2012/3/23
The previous I-cache timing attacks on RSA which exploit the instruction path of a cipher were mostly proof-of-concept, and it is harder to put them into practice than D-cache timing attacks. We propo...
Collision Timing Attack when Breaking 42 AES ASIC Cores
implementation / Timing Attack Collision Attack Fault Sensitivity AES ASIC
2012/3/29
A collision timing attack which exploits the data-dependent timing characteristics of combinational circuits is demonstrated. The attack is based on the correlation collision attack presented at CHES ...
An Improved Timing Attack with Error Detection on RSA-CRT
Timing attack RSA T-test Montgomery reduction
2010/2/20
Several types of timing attacks have been published, but they are either in theory or hard to be taken into practice. In order to improve the feasibility of attack, this paper proposes an advance timi...
We present a bitsliced implementation of AES encryption in counter mode for 64-bit
Intel processors. Running at 7.81 cycles/byte on a Core 2, it is up to 25% faster than previous
implementations, wh...