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A High Throughput/Gate AES Hardware Architecture by Compressing Encryption and Decryption Datapaths --- Toward Efficient CBC-Mode Implementation
AES hardware architectures unified encryption/decryption processors
2016/6/8
This paper proposes a highly efficient AES hardware architecture that supports both encryption and decryption for the CBC mode. Some conventional AES architectures employ pipelining techniques to enha...
We present a hardware architecture for all building blocks required
in polynomial ring based fully homomorphic schemes and use it to
instantiate the somewhat homomorphic encryption scheme YASHE. Our...
Efficient and Low-complexity Hardware Architecture of Gaussian Normal Basis Multiplication over GF(2m) for Elliptic Curve Cryptosystems
Finite Fields Elliptic Curve Cryptosystems Multiplication
2015/12/21
In this paper an efficient high-speed architecture of Gaussian normal basis multiplier over binary finite
field GF(2m) is presented. The structure is constructed by using regular modules for computat...
A Low-Area Unified Hardware Architecture for the AES and the Cryptographic Hash Function ECHO
implementation / AES ECHO hash functions implementation SHA-3
2012/3/29
We propose a compact coprocessor for the AES (encryption, decryption, and key expansion) and the cryptographic hash function ECHO on Virtex-$5$ and Virtex-$6$ FPGAs. Our architecture is built around a...
A Low-Area Unified Hardware Architecture for the AES and the Cryptographic Hash Function ECHO
AES ECHO hash functions implementation SHA-3
2011/2/24
We propose a compact coprocessor for the AES (encryption, decryption, and key expansion) and the cryptographic hash function ECHO on Virtex-$5$ and Virtex-$6$ FPGAs. Our architecture is built around a...
Divide and Concatenate: A Scalable Hardware Architecture for Universal MAC
Scalable Hardware Architecture Universal MAC
2009/4/10
We present a cryptographic architecture optimization
technique called divide-and-concatenate based on two
observations: (i) the area of a multiplier and associated data
path decreases exponentially...
In AVS-P2 video compression standard, similar to MPEG-2, entropy coding firstly assembles two
dimensional coefficients of each block into a sequence of (Run, Level) combinations serially. As we know,...
An Optimized Hardware Architecture of Montgomery Multiplication Algorithm
Montgomery Multiplication MWR2MM Algorithm Field Programmable Gate Arrays
2008/8/21
Montgomery multiplication is one of the fundamental op-
erations used in cryptographic algorithms, such as RSA and Elliptic
Curve Cryptosystems. At CHES 1999, Tenca and Ko»c introduced a now-
...
Hardware Architecture for AVS Entropy Encoder
AVS-P2 Entropy Coding VLC Contextbased Hardware Pipeline
2013/7/17
In AVS-P2 video compression standard, similar to MPEG-2, entropy coding firstly assembles two dimensional coefficients of each block into a sequence of (Run, Level) combinations serially. As we know, ...