搜索结果: 16-21 共查到“军事学 high speed”相关记录21条 . 查询时间(0.203 秒)
A High Speed Pairing Coprocessor Using RNS and Lazy Reduction
implementation / RNS Moduli Selection Hardware Implementation of Pairing FPGA
2012/3/28
In this paper, we present a high speed pairing coprocessor using Residue Number System (RNS) and lazy reduction. We show that combining RNS, which are naturally suitable for parallel architectures, an...
A High Speed Pairing Coprocessor Using RNS and Lazy Reduction
implementation RNS Moduli Selection Hardware Implementation of Pairing FPGA
2011/6/9
In this paper, we present a high speed pairing coprocessor using Residue Number System (RNS) and lazy reduction. We show that combining RNS, which are naturally suitable for parallel architectures, an...
High-Speed Software Implementation of the Optimal Ate Pairing over Barreto-Naehrig Curves
Tate pairing optimal pairing Barreto{Naehrig curve ordinary curve
2010/7/14
This paper describes the design of a fast software library for the computation of the optimal ate pairing on a Barreto--Naehrig elliptic curve. Our library is able to compute the optimal ate pairing o...
Efficient Techniques for High-Speed Elliptic Curve Cryptography
implementation Elliptic curve cryptosystem point multiplication point operation field arithmetic software implementation x86-64 processor
2010/7/13
In this paper, a thorough bottom-up optimization process (field, point and scalar arithmetic) is used to speed up the computation of elliptic curve point multiplication and report new speed records on...
High-Speed Hardware Implementations of BLAKE, Blue Midnight Wish, CubeHash,ECHO, Fugue, Gr stl, Hamsi, JH, Keccak,Lu a, Shabal, SHAvite-3, SIMD, and Skein Version 2.0, November 11, 2009
SHA-3 round 2 hardware
2009/11/18
In this paper we describe our high-speed hardware implementations
of the 14 candidates of the second evaluation round of the
SHA-3 hash function competition. We synthesized all implementations
usin...
High Speed Architecture for Galois/Counter Mode of Operation（GCM）
High Speed Architecture Galois/Counter Mode GCM
2009/2/7
In this paper we present a fully pipelined high speed hardware architecture
for Galois/Counter Mode of Operation (GCM) by analyzing the data
dependencies in the GCM algorithm at the architecture lev...