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An Efficient VLSI Architecture for Motion Compensation of AVS HDTV Decoder
VLSI Architecture Motion Compensation AVS HDTV Decoder
2010/12/16
An Efficient VLSI Architecture for Motion Compensation of AVS HDTV Decoder.
An Efficient VLSI Architecture for MC Interpolation in AVC Video Coding
VLSI Architecture MC Interpolation AVC Video Coding
2010/12/14
Video Coding (AVC) has employed a 6-tap interpolation FIR filter in its motion compensation (MC) part for high coding efficiency. But it is accompanied by increasing the complexity in calculation and ...