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An Efficient VLSI Architecture of VLD for AVS HDTV Decoder
VLSI Architecture VLD AVS HDTV Decoder
2010/12/16
!aIn this paper, we present a VLSI design of Variable Length Code Decoder for AVS video standard. As a co-processor of a RISC CPU, the design can decode Fixed Length Code, unsigned or signed k-th Exp-...
A PLATFORM-BASED ARCHITECTURE OF LOOP FILTER FOR AVS
PLATFORM-BASED ARCHITECTURE LOOP FILTER FOR AVS
2010/12/14
AVS is Chinese new audio and video coding standard, in which a loop filter has been applied to remove blocking artifacts. A platform-based architecture for the loop filter of AVS standard is proposed ...
AN IMPLEMENTED ARCHITECTURE OF DEBLOCKING FILTER FOR H.264/AVC
IMPLEMENTED ARCHITECTURE DEBLOCKING FILTER H.264/AVC
2010/12/14
H.264/AVC is a new international standard for the compression of natural video images, in which a deblocking filter has been adopted to remove blocking artifacts. In this paper, we propose an efficien...
An Efficient VLSI Architecture of the Sample Interpolation for MPEG-4 Advanced Simple Profile
Efficient VLSI Architecture the Sample Interpolation MPEG-4 Advanced Simple Profile
2010/12/14
Sample interpolation which has a computationally expensive finite impulse response (FIR) digital filter is one of the key modules in MPEG-4 Advanced Simple Profile (ASP). Normal FIR architectures have...